Nonvolatile semiconductor memory devices such as a NAND flash memory are increasingly downscaled in order to expand memory capacities. With increased downscaling, distances between adjacent memory cells are shortened, which causes considerable interference and the like (hereinafter, “proximity effect”) between the memory cells. The proximity effect adversely increases a width of a threshold voltage distribution of the memory cells in which data are written.
Meanwhile, as the memory is downscaled, it is preferable that voltages to be applied during writing and reading are lowered. However, when the width of the threshold voltage distribution of the memory cells is increased, distances between data (voltage differences) need to be increased and the voltages applied during writing and reading become rather higher. Therefore, differences between threshold voltages of the memory cells after data writing and threshold voltages of the memory cells after data erasing become larger. As a result, the interference (proximity effect) between the adjacent memory cells is increased and the width of the threshold voltage distribution is further increased.
Even when the width of the threshold voltage distribution becomes larger, increases in writing or reading voltages can be suppressed by using an ECC (Error Correcting Code). However, the ECC with a high correcting capability requires many redundant columns, which increases the number of gates in an ECC circuit. This leads to an increase in a chip size of the memory and costs thereof.
A multi-level storage memory in which each memory cell stores therein two or more bits of data achieve one data writing in two or more stages to reduce the proximity effect. In this case, a writing stage is sometimes performed for memory cells MCn−1 and MCn+1 adjacent to the memory cell MCn between first and second writing stages for a memory cell MCn connected to a word line WLn. Accordingly, threshold voltages of the memory cells MCn−1 and MCn+1 in the second writing stage for the memory cell MCn become higher than threshold voltages of the memory cells MCn−1 and MCn+1 in the first writing stage for the memory cell MCn in some cases. In these cases, resistances of the memory cells MCn−1 and MCn+1 during verify reading of the second writing stage for the memory MCn are higher than those during verify reading of the first writing stage. Accordingly, currents (cell currents) flowing through the selected memory cells MCn are varied due to influences of the adjacent memory cells MCn−1 and MCn+1. This is also a factor that increases the width of the threshold voltage distribution.